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AIman

 Jabaren

PhD Student at UCSD

A

I am a Ph.D. student at the Electrical and Computer Engineering department at the University of California, San Diego. I work at the Video Processing Lab under the supervision of Prof. Troung Nguyen. My research involves sovling computer vision problems using Machine Learning and Deep Learning. 

My Master's Thesis involves classifying and rating Tennis Serves performance using Machine Learning.  Other current Projects include developing depth estimation algorithms using single camera and image dehazing using state of the art Unet Neural Network and Wavelets Filterbank architecture. 

 

Previous experience include problem-solving in different fields of engineering, mainly: SoC and ethernet controller R&D projects in the high-tech industry, and other engineering projects in incubator environments and Hackathons. Engineering experiences include signal and image processing and developing meticulous verification plans and tests leading to the early discovery of design bugs.

 

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DOWNLOAD RESUME

01 PROFESSIONAL

Technical Competencies

Machine Learning • Signal Processing • Image Processing  

Computer Vision • Algorithms • Electrical Engineering • Bio-medical Engineering

  Pre-silicon Verification • Post-silicon Validation

70%

85%

80%

85%

80%

02 PORTFOLIO

MY LATEST WORK. SEE MORE >

03 Experience

2016-Present

Intel Corporation

Architecture Verification Engineer

ï‚· Research chip design, architecture; wrote test plans; coded, ran tests; verified full coverage.
ï‚· Chart path for fixing bugs before production
ï‚· Initiate tests and optimize test performance, running time, thus freeing server slots 

2015-2016

Intel Corporation

Electrical Verification Engineer

Designed, implemented, debugged post-silicon chip validation tests in lab environment 

2012-2013

Neural Interface Engineering Laboratory, Bio-Medical Engineering Faculty, Technion

Research Assistance

Set up new optical 3D microscopic system to be used for neural research and development at the Neural Interface Engineering Lab 

2011-2013

Landa Project, Technion

Teaching Assistant

Wrote lessons from scratch, taught and tutored first year calculus in classes and private lessons. 

CONTACT

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ayjabi@gmail.com

Tel: +1-8582509330

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  • LinkedIn
  • github
CONTACT
PROFESSIONAL 
PORTFOLIO
EXPERIENCEO

02 PORTFOLIO

MY LATEST WORK. SEE MORE >

03 Experience

2016-2018

Intel Corporation

Architecture Verification Engineer

ï‚· Research chip design, architecture; wrote test plans; coded, ran tests; verified full coverage.
ï‚· Chart path for fixing bugs before production
ï‚· Initiate tests and optimize test performance, running time, thus freeing server slots 

2015-2016

Intel Corporation

Electrical Verification Engineer

Designed, implemented, debugged post-silicon chip validation tests in lab environment 

2012-2013

Neural Interface Engineering Laboratory, Bio-Medical Engineering Faculty, Technion

Research Assistance

Set up new optical 3D microscopic system to be used for neural research and development at the Neural Interface Engineering Lab 

2011-2013

Technion Institute of Technology

Calculus Teaching Assistant

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06-08/2009

Visual Attention Lab - Harvard Medical School and Brigham and
Women’s Hospital

Research Assistant

Studied 2-Dimensional vs 3-Dimensional eye tracking

02 Research

MY LATEST WORK. SEE MORE >

03 Experience

2019-Present

Video Processing Lab, UCSD

                                          Research Staff

  • Develop Tennis shots classifier using machine learning

  • Extract human joints coordinates using ML and different LSTM architectures for joints series classification

  • Outperformed state of the art image dehazing U-net Neural Network through multi-level Wavelet Filterbank feature extraction

2016-2018

Intel Corporation

Architecture Verification Engineer

  •  Research chip design, architecture; wrote test plans; coded, ran tests; verified full coverage.

  • Chart path for fixing bugs before production

  • Initiate tests and optimize test performance, running time, thus freeing server slots 

2015-2016

Intel Corporation

Electrical Verification Engineer

Designed, implemented, debugged post-silicon chip validation tests in lab environment 

2012-2013

Neural Interface Engineering Laboratory, Bio-Medical Engineering Faculty, Technion

Research Assistance

Set up new optical 3D microscopic system to be used for neural research and development at the Neural Interface Engineering Lab 

2011-2013

Technion Institute of Technology

Calculus Teaching Assistant

​

06-08/2009

Visual Attention Lab - Harvard Medical School and Brigham and
Women’s Hospital

Research Assistant

Studied 2-Dimensional vs 3-Dimensional eye tracking

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